Method of rewriting data of memory device, memory controller controlling the memory device, and controlling method of the memory controller

ABSTRACT

A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2018-0167887, filed on Dec. 21, 2018,in the Korean Intellectual Property Office, and entitled: “Method ofRewriting Data of Memory Device, Memory Controller Controlling theMemory Device, and Controlling Method of the Memory Controller,” isincorporated by reference herein in its entirety.

BACKGROUND 1. Field

Embodiments relate to a method of rewriting data of a memory device, amemory controller, and a method of controlling the memory device byusing the memory controller, and more particularly, to a memory devicefor performing data rewrite operations, a memory controller forcontrolling the memory device, and a controlling method of the memorycontroller.

2. Description of the Related Art

As non-volatile memory devices, including flash memory, resistive memorydevices such as phase-change RAM (PRAM), Nano-Floating Gate memory(NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM(FeRAM), resistive RAM (RRAM) are well known. A resistive memory has ahigh speed of DRAM and a non-volatile characteristic of a flash memory.

In the resistive memory, fluctuation in a threshold voltage orfluctuation in a resistance distribution of the memory cells may berelatively great. As fluctuation in the resistance distribution of thememory cells may cause errors in data read operations, a method ofcompensating for fluctuation in the resistance distribution is required.

SUMMARY

According to an aspect, there is provided a memory controller configuredto control a memory device, the memory controller including: an ErrorChecking and Correcting (ECC) engine configured to perform errordetection on data read from the memory device; and a data operationmanager configured to control a first rewrite operation of the memorydevice on selected memory cells to compensate for a drift in adistribution of selected memory cells, based on a result of a test readoperation of the memory device on test cells, determine a distributionadjustment degree based on a result of a normal read operation, as anECC decoding operation by using the engine, which corresponds to thenormal read operation of the memory device, is successfully performed,and control a second rewrite operation of the memory device based on thedetermined distribution adjustment degree.

According to another aspect, there is provided a controlling method of amemory controller, the method including: controlling, based on a resultof a test read operation on test cells stored in a memory device, afirst rewrite operation of the memory device to compensate for a driftin a distribution with respect to selected memory cells; controlling anormal read operation of the memory device performed by using a normalread pulse on the selected memory cells; and controlling, based on adistribution adjustment degree determined according to a result of thenormal read operation, a second rewrite operation of the memory devicewith respect to the selected memory cells.

According to another aspect, a method of rewriting data of a memorydevice may include: performing, on selected memory cells, a normal datawrite operation including a normal reset operation to form a reset-statenormal distribution by using a normal reset pulse and a normal setoperation to form a set-state normal distribution by using a normal setpulse; performing a partial rewrite operation on the selected memorycells for compensating for the drift when the drift in the distributionin the memory cells is detected according to a test read operation ontest cells; performing a normal read operation on the selected memorycells by using a normal read pulse; identifying a direction of thedegradation in the distribution of the memory cells, the directionidentified according to the performing of the normal read operation; andperforming an adaptive rewrite operation for forming distributions at adirection opposite the identified direction of the degradation, based onthe normal distribution in the reset-state and the normal distributionin the set-state.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describingin detail exemplary embodiments with reference to the attached drawingsin which:

FIG. 1 illustrates a data processing system according to an exampleembodiment;

FIG. 2 illustrates a memory controller according to an exampleembodiment;

FIG. 3 illustrates a memory device according to an example embodiment;

FIGS. 4A and 4B illustrate circuit diagrams as an example of a memorycell array;

FIGS. 5A through 5C each illustrate a graph of pulses according to time,the pulses for a normal reset operation, a normal set operation, and anormal read operation;

FIGS. 6A and 6B each illustrate a graph for describing degradation of adistribution;

FIG. 7 illustrates a flowchart for describing a controlling method of amemory controller, according to an example embodiment;

FIG. 8 illustrates a memory system according to an example embodiment:

FIG. 9 illustrates a flowchart for describing a method of controlling afirst rewrite operation;

FIGS. 10A and 10B each illustrate a distribution of memory cells fordescribing a first condition;

FIG. 11 illustrates a graph of a partial rewrite pulse and a normal readpulse according to time, according to an example embodiment;

FIG. 12 illustrates a graph of a partial rewrite pulse according totime, a graph of a cell current according to time, and a change in thedistribution, according to an example embodiment;

FIG. 13 illustrates a memory system according to an example embodiment;

FIG. 14 illustrates a flowchart of a method of controlling a secondrewriting operation;

FIG. 15 illustrates a distribution of memory cells for describing asecond condition, according to an example embodiment;

FIG. 16 illustrates a flowchart of a method of controlling a secondrewrite operation;

FIG. 17 illustrates a graph of an adaptive reset pulse, an adaptive setpulse, a normal reset pulse, and a normal set pulse over time;

FIG. 18 illustrates a graph of the adaptive set pulse and fluctuation ina distribution over time;

FIG. 19 illustrates a graph of the adaptive reset pulse and fluctuationin a distribution over time;

FIG. 20 illustrates a distribution of the memory cells for describingthe second condition according to an example embodiment;

FIG. 21 illustrates a flowchart of a method of controlling a secondrewrite operation;

FIGS. 22A and 22B illustrate distribution adjustment informationaccording to an example embodiment; and

FIG. 23 illustrates a flowchart of a controlling method of the memorycontroller.

DETAILED DESCRIPTION

FIG. 1 illustrates a data processing system 10 according to an exampleembodiment. The data processing system 10 may include a host 100 and amemory system 400. The memory system 400 may include a memory controller200 and a memory device 300. The data processing system 10 may be usedfor one of various electronic devices, e.g., an ultra mobile PC (UMPC),a workstation, a Netbook, a personal digital assistant (PDA), a portablecomputer, a web tablet, a wireless phone, a mobile phone, a smart phone,an e-book, a portable multimedia player (PMP), a handheld game console,a navigation system, a black box, a digital camera, and so on.

The data processing system 10 may be embodied in various forms. Forexample, the host 100, the memory controller 200, and the memory device300 may each be provided as a chip, a package, or a module. However, inan implementation, the memory controller 200, together with the memorydevice 300, may be provided as the memory system 400 or a storagedevice.

In addition, the memory system 400 may be included in a PC card, aCompactFlash card, a smart media card, a memory stick, a multi-mediacard (MMC), an SD card, a universal flash storage (UFS), and the like.In an embodiment, the memory system 400 may be included in a solid statedisk/drive (SSD). Hereinafter, for convenience of explanation, it isassumed that the memory system 400 is embodied as a storage device.

The host 100 may transmit a data operation request REQ and an addressADDR to the memory controller 200 and may also exchange data DATA withthe memory controller 200. The host 100 and the memory controller 200may communicate with each other through various protocols. For example,the host 100 and the memory controller 200 may communicate with eachother through at least one of various interface protocols such as auniversal storage bus (USB) protocol, a multi-media card (MMC) protocol,a peripheral component interconnect express (PCI-E) protocol, anadvanced technology attachment (ATA) protocol, a serial-ATA protocol, aparallel-ATA protocol, a small computer system interface (SCSI)protocol, an enhanced small device interface (ESDI) protocol, and anintegrated drive electronics (IDE) protocol.

The memory controller 200 may control the memory device 300. Forexample, the memory controller 200 may, in response to a data operationrequest REQ received from the host 100, control the memory device 300 toread data DATA stored in the memory device 300 or write data DATA to thememory device 300. The memory controller 200 may, by providing anaddress ADDR, a command CMD, and control signals to the memory device300, control data operations including write operations and readoperations of the memory device 300. In addition, data DATA for theabove-mentioned data operations may be transmitted or received betweenthe memory controller 200 and the memory device 300.

The memory device 300 may include a memory cell array 310 and aread/write circuit 360. In an embodiment, the memory cell array 310 mayinclude resistive memory cells and, in this case, the memory device 300may be referred to as “a resistive memory device”. Hereinafter, anembodiment in which the memory device 300 is a resistive memory devicewill be mainly described. However, embodiments may also be applied tovarious kinds of memory devices including a non-volatile memory device,e.g., a flash memory device, or a volatile memory device.

The read/write circuit 360, which is connected to the memory cell array310 through bit lines and/or word lines, may write data to a memory cellor read data from the memory cell. In an embodiment, the read/writecircuit 360 may be connected to a plurality of word lines and/or aplurality of bit lines and write or read data. For example, in a readoperation, the read/write circuit 360 may apply a voltage correspondingto a read pulse to the selected memory cell; and in a write operation,the read/write circuit 360 may apply a current corresponding to a resetpulse or a set pulse to the selected memory cell.

The memory controller 200 according to an embodiment may include a dataoperation manager 240 and may also store condition information CI anddistribution adjustment information DAI.

The data operation manager 240 may control data operations, e.g., a readoperation and a write operation, of the memory device 300. The dataoperation manager 240 may be referred to as a data operation managementcircuit. In an embodiment, the data operation manager 240 may controlrewrite operations of the memory device 300. The rewrite operations mayinclude a first rewrite operation and a second rewrite operation. Thefirst rewrite operation, which may also be referred to as a partialrewrite operation, indicates a data operation for compensating for adrift in a resistance distribution of memory cells. The first rewriteoperation will be described in more detail with reference to FIGS. 8through 12. The second rewrite operation, which may be referred to as anadaptive rewrite operation, indicates a data operation to adaptivelyrewrite data according to characteristics of the memory cells. Thesecond rewrite operation will be described in more detail with referenceto FIGS. 13 through 22B hereinafter.

Throughout the specification, for distinction from the first rewriteoperation and the second rewrite operation, a read operation and a writeoperation, which are general, may respectively be referred to as anormal read operation and a normal write operation. Throughout thespecification, for convenience of explanation, a resistance distributionof the memory cells will be in short referred to as a distribution ofmemory cells.

In an embodiment, based on a result of a test read operation on testcells stored in the memory cell array 310, the data operation manager240 may control the first rewrite operation of the memory device 300.For example, the data operation manager 240 may identify thedistribution of the memory cells using the result of the test readoperation. When the distribution of the test cells fulfills a firstcondition that indicates degradation of the distribution, the dataoperation manager 240 may control the memory device 300 to perform thefirst rewrite operation. The first condition, which may be included inthe condition information CI, may include a case in which the number oferror cells detected in the test read operation using a first read levelis greater than a first threshold value and a case in which the numberof on cells corresponding to the test read operation using a second readlevel is greater than a second threshold value. The first read level maybe equal or similar to a normal read level. A value of the second readlevel may be greater than a value of the first read level.

In the first rewrite operation of the memory device 300, the dataoperation manager 240 may control the memory device 300 to apply avoltage corresponding to a partial rewrite pulse to selected memorycells. In an embodiment, compared to the normal read pulse, the partialrewrite pulse may have a higher voltage level and a shorter duration.However, in an implementation, the voltage level of the partial rewritepulse may be similar to or lower than a voltage level of the normal readpulse. In addition, in an implementation, the duration of the partialrewrite pulse may be equal to or similar to a time period consumed forprecharge during the normal read operation. In an implementation, thevoltage level of the partial rewrite pulse may be lower than a voltagelevel of a pulse used in the write operation.

The data operation manager 240 may control the normal read operation ofthe memory device 300 on the selected memory cells stored in the memorycell array 310.

The data operation manager 240 may identify a distribution of theselected memory cells by using the result of the normal read operationand determine a distribution adjustment degree based on the distributionof the selected memory cells. The distribution adjustment degree mayindicate a degree by which the distribution of the memory cells isadjusted in the second rewrite operation of the memory device 300. In animplementation, when set-state memory cells from among the selectedmemory cells have a resistance distribution higher than a set-statenormal distribution, the data operation manager 240 may determine thedistribution adjustment degree such that the set-state memory cells fromamong the selected memory cells have a resistance distribution lowerthan the set-state normal distribution. In an implementation, the dataoperation manager 240 may determine the distribution adjustment degreebased on the distribution adjustment information DAI. Likewise, in animplementation, when reset-state memory cells from among the selectedmemory cells have a resistance distribution lower than a reset-statenormal distribution, the data operation manager 240 may determine thedistribution adjustment degree such that the reset-state memory cellsfrom among the selected memory cells have a resistance distributionhigher than the reset-state normal distribution.

Here, the set-state normal distribution may indicate a distributionbefore degradation, after a normal set operation using a normal setpulse is performed on the memory cells. Likewise, the reset-state normaldistribution may indicate a distribution before degradation, after anormal reset operation by using a normal reset pulse is performed on thememory cells. In other words, the set-state normal distribution mayindicate an ideal distribution of the set-state memory cells and thereset-state normal distribution may indicate an ideal distribution ofthe reset-state memory cells.

The data operation manager 240 may control the second rewrite operationof the memory device 300 based on the determined distribution adjustmentdegree. The second rewrite operation may be performed in a DataComparison Write (DCW) off mode.

By using the data processing system 10 according to an exampleembodiment, the first rewrite operation of the memory device 300 may becontrolled based on the result of the test operation on the test cells,fluctuation (or degradation) in the distribution of the memory cells maybe compensated for by controlling the second rewrite operation based onthe result of the normal read operation, and read errors due to thefluctuation in the distribution of the memory cells may be reduced.

In addition, the memory cells may respectively have differentcharacteristics (e.g., a drift characteristic, a characteristic of beinginfluenced by neighboring cells, etc.). By performing the second rewriteoperation to adjust a position of the distribution consideringfluctuation (or degradation) of a future distribution, the dataprocessing system 10 according to an example embodiment may adaptivelycontrol the characteristics of the memory cells.

FIG. 2 illustrates the memory controller 200 according to an exampleembodiment. The memory controller 200 may include a system bus 210, theprocessor 220, an internal memory 230, the data operation manager 240,an Error Checking and Correcting (ECC) engine 250, a host interface 260,and a memory interface 270. The memory controller 200 may furtherinclude various components, e.g., a command generating module thatgenerates commands CMD for controlling memory operations. Regarding thememory controller 200, descriptions previously given with reference toFIG. 1 will be omitted. FIG. 2 is described with reference to FIG. 1.

The system bus 210 may provide a channel between internal components ofthe memory controller 200. The system bus 210 may be operated based onone of various bus protocols.

The processor 220 may control all operations of the memory controller200. The processor 220 may include at least one processing device, e.g.,a Central Processing Unit (CPU), a Micro-Processing Unit (MCU), and thelike. The processor 220 may drive software and/or firmware to controlthe memory controller 200. For example, a portion of the software and/orfirmware may be loaded in the internal memory 230 and be driven by theprocessor 220.

The internal memory 230 may be used as one of various memories, e.g., anoperation memory, a buffer memory, a cache memory, and so on. For this,the internal memory 230 may be embodied in various memories, e.g., atleast one of dynamic random access memory (DRAM), static random accessmemory (SRAM), phase-change random access memory (PRAM), a flash memory,and the like.

The internal memory 230 according to an example embodiment may store thecondition information CI and the distribution adjustment informationDAI. In an implementation, the control information CI may include firstcondition information for determining whether to perform the firstrewrite operation and second condition information for determiningwhether to perform the second rewrite operation. The first conditioninformation for determining whether to perform the first rewriteoperation may be referred to as a first condition. The second conditioninformation for determining whether to perform the second rewriteoperation may be referred to as a second condition.

The first condition will be described in more detail with reference toFIGS. 10A and 10B, and the second condition will be described in moredetail with reference to FIGS. 15 to 20. The distribution adjustmentinformation DAI is information used for determining the distributionadjustment degree. The distribution adjustment information DAI will bedescribed in more detail with reference to FIGS. 22A and 22B.

The data operation manager 240 may control the data operations of thememory device 300. The data operation manager 240 may include a firstrewrite manager 242 and a second rewrite manager 244. The first rewritemanager 242 may control the first rewrite operation of the memory device300. The second rewrite manager 244 may control the second rewriteoperation of the memory device 300.

The data operation manager 240 may be embodied in various forms in thememory controller 200 and, according to embodiments, the data operationmanager 240 may be embodied in the form of hardware or software. Forexample, when the data operation manager 240 is embodied in the form ofhardware, the data operation manager 240 may include circuits forcontrolling the data operations of the memory device 300. As anotherexample, when the data operation manager 240 is embodied in the form ofsoftware, programs (or instructions) stored in the memory controller 200may be executed by the processor 220, and thus, the data operations maybe controlled. In an implementation, the data operation manager 240 maybe embodied in a combination of software and hardware, like firmware. Inan embodiment, the data operation manager 240 may, completely orpartially, be included in a Flash Translation Layer (FTL).

The ECC engine 250 may perform an operation of checking and correctingerrors of data DATA read from the memory device 300. The operation ofchecking and correcting errors may be referred to as an ECC decodingoperation. For example, the data DATA read from the memory device 300may include normal data and parity data that construct a code word. TheECC engine 250 may perform the ECC decoding operation by using theparity data.

The host interface 260 may provide an interface between the host 100 andthe memory controller 200. The memory controller 200 may, via the hostinterface 260, receive the data operation request REQ, the address ADDR,and the like from the host 100 and may exchange the data DATA with thehost 100.

The memory interface 270 may provide an interface between the memorydevice 300 and the memory controller 200. For example, the data DATAprocessed by the processor 220 may be stored in the memory device 300via the memory interface 270. Alternatively, the data DATA stored in thememory device 300 may be provided to the processor 220 via the memoryinterface 270. The memory controller 200 may transmit the command CMD,the address ADDR, and the like to the memory device 300 via the memoryinterface 270 and may also exchange the data DATA with the memory device300.

By using the memory controller 200, the rewrite operation of the memorydevice 300 may be controlled based on the result of the test operationon test cells, fluctuation (or degradation) in the distribution of thememory cells may be compensated for by controlling the second rewriteoperation based on the result of the normal read operation, and readerrors due to the fluctuation in the distribution of the memory cellsmay be reduced.

In addition, the memory cells may respectively have differentcharacteristics (e.g., a drift characteristic, a characteristic of beinginfluenced by neighboring cells, etc.). By performing the second rewriteoperation to adjust the position of the distribution considering thefluctuation (or degradation) in the future distribution, based on theresult of the normal read operation, the memory controller 200 mayadaptively control the characteristics of the memory cells.

FIG. 3 illustrates the memory device 300 according to an exampleembodiment. The memory device 300 may include the memory cell array 310,a row decoder 320, a column decoder 330, a voltage generator 340, acontrol logic 350, and a read/write circuit 360. Regarding the memorydevice 300 of FIG. 3, descriptions previously given with reference toFIG. 1 are omitted. FIG. 3 is described with reference to FIG. 1.

The memory cell array 310 may include a plurality of memory cellsrespectively located where a plurality of first signal lines and aplurality of second signal lines intersect one another. In an exampleembodiment, the plurality of first signal lines may be word lines WLs,and the plurality of second signal lines may be bit lines BLs. Thememory device 300 including the memory cell array 310 may be referred toas a cross-point memory device. In an embodiment, the memory cell array310 may have a same structure as shown in FIGS. 4A and 4B.

The row decoder 320 may select some of the word lines WLs based on a rowaddress X-ADDR provided by the control logic 350. The row decoder 320may provide a voltage to word lines. The column decoder 330 may selectsome of the bit lines BLs based on a column address Y-ADDR provided bythe control logic 350.

The voltage generator 340 may generate various kinds of voltages neededby the memory device based on a voltage control signal CTRL_vol providedby the control logic 350. For example, the voltage generator 340 maygenerate a write voltage Vwrite used for the write operation and a readvoltage Vread used for the read operation. The write voltage Vwrite andthe read voltage Vread may be provided to the bit line and/or word line.Furthermore, in an embodiment, the voltage generator 340 may generatevoltages required for the first rewrite operation and the second rewriteoperation.

The control logic 350 may, based on a command CMD, an address ADDR, anda control signal CTRL received from the memory controller 200, generatevarious internal control signals for writing data to the memory cellarray 310 or reading data from the memory cell array 310. In otherwords, the control logic 350 may control all operations of the memorydevice 300. The various internal control signals generated in thecontrol logic 350 may be provided to the row decoder 320, the columndecoder 330, the voltage generator 340, and the like. For example, thecontrol logic 350 may provide the row address X-ADDR to the row decoder320, the column address Y-ADDR to the column decoder 330, and thevoltage control signal CTRL_vol to the voltage generator 340.

The read/write circuit 360 may perform a read operation and a writeoperation on the memory cells. The read/write circuit 360 may beconnected to the memory cells through the bit lines BL and may include awrite driver for writing data to the memory cells, and a senseamplifier.

FIG. 3 illustrates a case in which the read/write circuit 360 isconnected to the memory cell array 310 via the bit lines BLs. However,according to embodiments, the read/write circuit 360 may be connected tothe memory cell array 310 via the word lines WLs. In this case, that thesignal lines connected to the read/write circuit 360 are not the bitlines BLs, but the word lines WLs.

The memory device 300 according to an example embodiment may, undercontrol of the memory controller 200, perform the test read operation,the first rewrite operation, the normal read operation, and the secondrewrite operation.

The memory device 300 performs the first rewrite operation based on theresult of the test read operation on the test cells and performs thesecond write operation based on the result of the normal read operation.Thus, the fluctuation (or degradation) in the distribution of the memorycells may be compensated and read errors occurring due to thefluctuation in the distribution of the memory cells may be reduced.

The memory cells may respectively have different characteristics. Byperforming the second rewrite operation based on the result of thenormal read operation to adjust the position of the distributionconsidering the fluctuation (or degradation) in the future distribution,the memory controller 200 may adaptively control the characteristics ofthe memory cells.

FIGS. 4A and 4B illustrate circuit diagrams of an embodiment of thememory cell array 310. FIGS. 4A and 4B each illustrate a case in whichthe memory cell is PRAM. The memory cell array 310 shown in FIG. 4A maycorrespond to a cell block.

The memory cell array 310 may be a two-dimensional memory cell arrayhaving a horizontal structure including a plurality of word lines WL1through WLn, a plurality of bit lines BL1 through BLm, and a pluralityof memory cells MC. The memory cell array 310 may include a plurality ofmemory blocks. In each memory block, a plurality of memory cells may bearranged in rows and columns. Here, the number of word lines WLs, thenumber of bit lines BLs, and the number of memory cells MC may bevariously modified according. In an implementation, the memory cellarray 310 may be a three-dimensional memory cell array having a verticalstructure.

According to the embodiment, the plurality of memory cells MC may eachinclude a variable resistor device R and a switching device SW. Here,the variable resistor device R may be referred to as a variable resistormaterial and the switching device SW may be referred to as a selectiondevice.

In an embodiment, the variable resistor device R is connected betweenone of the plurality of bit lines BL1 through BLm and the switchingdevice SW, and the switching device SW may be connected between thevariable resistor device R and one of the plurality of word lines WL1through WLn. However, in an implementation, the switching device SW maybe connected between one of the plurality of bit lines BL1 through BLmand the variable resistor device R, and the variable resistor device Rmay be connected between the switching device SW and one of theplurality of word lines WL1 through WLn.

The switching device SW may be connected between one of the plurality ofword lines WL1 through WLn and the variable resistor device R, and maycontrol a current supply to the variable resistor device R in responseto a voltage applied to the word line and the bit line connected to thevariable resistor device R. FIG. 4A shows a case in which the switchingdevice SW is a diode, but any appropriate switching device may be used.

Referring to FIG. 4B, the memory cell MC may include the variableresistor device R and the switching device SW. The switching device SWmay be embodied by using various devices such as a transistor or diode.The variable resistor device R may include a phase change layer 11including a combination of germanium (Ge), antimony (Sb), and tellurium(Te) (GST), an upper electrode 12 on the phase change layer 11, and alower electrode 13 under the phase change layer 11.

The upper electrode 12 and the lower electrode 13 may each includevarious kinds of metals, metal oxides, metal nitrides, or the like. Theupper electrode 12 and the lower electrode 13 may each include aluminum(Al), copper (Cu), titanium nitride (TiN), titanium-aluminum nitride(TixAlyNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au),polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalumnitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium(Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin(Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO₂), strontiumzirconate oxide (StZrO₃), and the like.

The phase change layer 11 may include a bipolar resistance memorymaterial or a unipolar resistance memory material. The bipolarresistance memory material may be programmed into a set-state or areset-state due to polarity of the material. Perovskite-based materialsmay be used for the bipolar resistance memory material. The unipolarresistance memory material may be programmed into the set-state or thereset-state by current having a same polarity, and a transition metaloxide, e.g., NiOx, TiOx, or the like, may be used for the unipolarresistance memory material.

The GST material may be programmed between an amorphous state having arelatively high resistivity and a crystalline state having a relativelylow resistivity. The GST material may be programmed by heating. Amagnitude and duration of heating may determine whether the GST materialremains in the amorphous or crystalline state. The high resistivity andlow resistivity may be represented by programmed values of logic “0” andlogic “1”, respectively, and may be detected by measuring theresistivity of the GST material. Conversely, the high resistivity andlow resistivity may be represented by the programmed values of logic “1”and logic “0”, respectively.

In FIG. 4B, when a write current I is applied to the memory cell MC, theapplied write current I flows through the lower electrode 13. When thewrite current I is applied to the memory cell MC for a very short periodof time, only a layer adjacent to the lower electrode 13 is heated byJoule's heat. At this time, due to a difference in heating profile, someof the phase change layer 11 may be in the crystalline state (or the setstate) or the amorphous state (or the reset state).

FIGS. 5A through 5C each illustrate a graph of pulses over time for anormal reset operation, a normal set operation, and a normal readoperation. FIGS. 5A through 5C are described with reference to FIGS. 1through 4B.

FIG. 5A particularly illustrates a time-temperature graph of memorycells in a write operation and a read operation. The write operation mayinclude a reset operation and a set operation. Referring to FIG. 5A, inthe reset operation, to make the phase change layer 11 be in theamorphous state (or a “RESET” state), a reset pulse is applied to thememory cell MC for a short period of time and then is removed. As thereset pulse is applied to the memory cell MC, a temperature of thememory cell MC becomes equal to or higher than a melting point Tmelt.When the reset pulse is removed, the temperature of the memory cell MCdrops. In the set operation, to make the phase change layer 11 be in thecrystalline state (or a “SET” state), a set pulse having a low level isapplied to the memory cell MC, and the applied set pulse is removedafter a period of time such that the phase change layer 11 iscrystallized. As the set pulse is applied to the memory cell MC, thetemperature of the memory cell MC becomes equal to or higher than acrystallization temperature Tcrys. As the set pulse is removed from thememory cell MC, the temperature of the memory cell MC drops. Therefore,based on the method above, the memory cell MC is set as one of thecrystalline state or the amorphous state. A level of the read pulse maybe lower than those of the set pulse and the reset pulse.

FIG. 5B particularly illustrates a time-current graph of the normalreset pulse for the normal reset operation and the normal set pulse forthe normal set operation. To generate a temperature pulse as shown inFIG. 5A, a pulse-type current as shown in FIG. 5B has to be applied tothe memory cell MC. Throughout the specification, a level of the pulsemay indicate a height of the pulse, and the duration of the pulse mayindicate a time over which the pulse is maintained, e.g., a width of thepulse. The duration of the pulse may also be referred to as a timeduration of the pulse.

To convert the memory cell MC into the RESET state, a currentcorresponding to the normal reset pulse is applied to the memory cellMC. The normal reset pulse may have a normal reset current level I_nrsand a normal reset time duration TD_nrs. To convert the memory cell MCinto the SET state, a current corresponding to the normal set pulse isapplied to the memory cell. The normal set pulse may havecharacteristics of a normal set current level I_ns and a normal set timeduration TD_ns. The normal set time duration TD_ns may be longer thanthe normal reset time duration TD_nrs, and the normal reset currentlevel I_nrs may be higher than the normal set current level I_ns. Inother words, the normal reset pulse may be higher and narrower than thenormal set pulse.

FIG. 5C particularly illustrates a time-voltage graph of the normal readpulse for the read operation. To distinguish the SET state and the RESETstate of the memory cell MC from each other, the memory device 300 mayapply a voltage of the normal read pulse to the memory cell MC. Thenormal read pulse may have a normal read voltage level V_nrd and anormal read time duration TD_nrd. The normal read voltage level V_nrdmay be greater than a SET state threshold voltage and less than a RESETstate threshold voltage.

FIGS. 6A and 6B each illustrate a graph for describing degradation ofdistribution according to an example embodiment. The memory cells MC mayindicate one of a first program state S1 and a second program state S2.The first program state S1 may be the SET state and the second programstate S2 may be the reset state.

FIG. 6A particularly illustrates a case in which the distribution isdegraded in a direction in which a resistance value of the distributionincreases, i.e., in which the distribution is degraded in the directionof a positive resistance axis. The first program state S1 and the secondprogram state S2 may respectively be converted into a degraded firstprogram state S1′ and a degraded second program state S2′. For example,a resistance level of the memory cell may increase over time or due tocontinuous stress, and the increase may be referred to as a drift ofresistance distribution. In FIG. 6A, when the memory device performs theread operation using a read voltage level corresponding to a referenceresistance Rref, a read error may occur due to memory cells included ina first area A1. The memory cells in the first area A1 may indicatememory cells which are converted from the original set-state to thereset-state due to degradation of the resistance distribution. Each ofthe memory cells in the first area A1 is referred to as a set-to-reset(STR) error cell. Due to degradation of distribution as shown in FIG.6A, the STR error cells may be generated. Thus, read errors may occur.

FIG. 6B particularly illustrates a case in which the resistancedistribution is degraded in a direction in which the resistance value ofthe distribution decreases, i.e., in which the distribution is degradedin the direction of a negative resistance axis. The first program stateS1 and the second program state S2 may respectively be converted into adegraded first program state S “and a degraded second program state S2”.For example, over time, the resistance level of the memory cell maydecrease due to the data operation performed on neighboring cells. InFIG. 6B, when the memory device performs the read operation using theread voltage level corresponding to the reference resistance Rref, aread error may occur due to memory cells included in a second area A2.The memory cells in the second area A2 may be memory cells which areconverted from the original reset-state to the set-state due to thedegradation of the resistance distribution. Each of the memory cells inthe second area A2 is referred to as a reset-to-set (RTS) error cell.Due to degradation of distribution as shown in FIG. 6B, the RTS errorcells may be generated. Thus, read errors may occur.

FIG. 7 is a flowchart for describing a controlling method of the memorycontroller. FIG. 7 is described with reference to FIGS. 1 through 3.

In operation S120, the memory controller 200 may control the memorydevice 300 to perform the first rewrite operation based on the result ofthe read operation on the test cells. In an embodiment, when the memorysystem is powered on after being powered off, the memory controller 200may control the test read operation of the memory device 300 performedon the test cells. The memory controller 200 may control the firstrewrite operation of the memory device 300 based on the result of thetest read operation. Operation S120 will be described in more detailwith reference to FIGS. 8 through 12.

In operation S140, the memory controller 200 may control the memorydevice 300 to perform the normal read operation. In other words, thememory controller 200 may control the normal read operation of thememory device 300.

In operation S160, the memory controller 200 may determine thedistribution adjustment degree based on the read result according to thenormal read operation. In an embodiment, the memory controller 200 mayidentify the direction of the distribution degradation of the memorycells by using the result of the normal read operation and may determinethe distribution adjustment degree such that the distribution is adirection that is opposite the direction of the distribution degradationidentified based on the normal state. The memory controller 200 maydetermine the distribution adjustment degree by using the distributionadjustment information DAI stored in the memory controller 200.

In operation S180, the memory controller 200 may control the memorydevice 300 to perform the second rewrite operation based on thedetermined distribution adjustment degree. In other words, the memorycontroller 200 may control the second rewrite operation of the memorydevice 300. Some characteristics of the second rewrite operation may bedifferent from those of the normal set operation and normal resetoperation according to a general normal write operation. For example, inthe second rewrite operation, a level and/or duration of the set pulsemay be different from a level and/or duration of the normal set pulse,or a level and/or duration of the reset pulse may be different from alevel and/or duration of the normal reset pulse. In an embodiment, thesecond rewrite operation may be performed in the DCW off mode. Forexample, the DCW off mode may refer to a mode in which data is writtenwithout comparing written data with data to be written.

Operations S160 and S180 will be described in more detail with referenceto FIGS. 13 through 22.

FIG. 8 illustrates the memory system 400 according to an exampleembodiment. More particularly, FIG. 8 illustrates configurations of thememory systems 400 for describing operation S120 shown in FIG. 7 in moredetail.

The memory controller 200 may include the first rewrite manager 242, theECC engine 250, and a cell counter 280, and may store the firstcondition information CI_1. The memory cell array 310 in the memorydevice 300 may include a test data area 312.

The first rewrite manager 242 may, when the memory system 400 is poweredon after being powered off, control the test read operation indicating aread operation on the test cells stored in the test data area 312. Theread test data may be provided to the memory controller 200. In anembodiment, the ECC engine 250 may perform an ECC decoding operation byusing pieces of test data and generate an ECC result Res_ECC. The ECCengine 250 may provide the ECC result Res_ECC to the first rewritemanager 242. In an embodiment, the ECC result Res_ECC may includeinformation regarding the number of error cells. In an embodiment, thecell counter 280 may perform a cell count operation by using the piecesof test data and provide a cell count result Res_CNT to the firstrewrite manager 242. The cell count result Res_CNT may includeinformation regarding the number of on cells.

Hereinafter, the reason for performing the test read operation when thememory system 400 is powered on after being powered off is described.The memory cell array 310 includes the plurality of memory cells whichare written at different times and have different characteristics.Therefore, reference cells for determining whether to perform the firstrewrite operation are needed. Accordingly, the memory cell array 310includes the test data area 312 to store the test cells and the memorydevice 300 performs the test read operation on the test cells. Accordingto the embodiment, the test read operation is performed when the memorysystem 400 is powered on again. In an implementation, the memorycontroller 200 may control the memory device 300 to perform the testread operation in each predetermined time cycle.

The first rewrite manager 242 may control the first rewrite operation ofthe memory device 300 based on the ECC result Res_ECC and/or the cellcount result Res_CNT. In an embodiment, the first rewrite manager 242may determine whether the first condition is fulfilled by comparing theECC result Res_ECC and/or the cell count result Res_CNT with the firstcondition information CI_1. When the first condition is fulfilled, thefirst rewrite manager 242 may control the first rewrite operation of thememory device 300. The first rewrite operation may be performed byapplying a voltage corresponding to the partial rewrite pulse, to theselected memory cells. Compared to the normal read pulse, the partialrewrite pulse may have a higher voltage level and a shorter duration.

FIG. 9 is a flowchart of a method of controlling the first rewriteoperation. FIG. 9 may particularly be a more detailed flowchart ofoperation S120 in FIG. 7. FIG. 9 is described with reference to FIG. 8.

In operation S122, the memory controller 200 may transmit a read commandfor the test cells stored in the test data area 312 to the memory device300. The memory device 300 may, in response to the read command, readpieces of test data from the test cells. The memory device 300 maytransmit the pieces of test data to the memory controller 200.

In operation S124, the memory controller 200 may receive the pieces oftest data from the memory device 300.

In operation S126, the memory controller 200 may determine whether adistribution of the pieces of test data fulfills the first conditionthat indicates degradation of the distribution. Whether the firstcondition is fulfilled will be described in more detail with referenceto FIGS. 10A and 10B.

In operation S128, when the first condition is fulfilled, the memorycontroller 200 may control the memory device 300 to perform the firstrewrite operation for compensating for the drift of the resistancedistribution.

FIGS. 10A and 10B each illustrate a distribution of the memory cells fordescribing the first condition according to an example embodiment. FIGS.10A and 10B are described with reference to FIG. 8.

FIG. 10A illustrates a method of determining whether the first conditionis fulfilled when the drift occurs in the distribution of theresistances of the memory cells. When the resistance distribution in thefirst program state S1 is degraded and changed into the resistancedistribution in the degraded first program state S1′, the ECC engine 250may, after performing the ECC decoding operation on test data that isread according to the test read operation by using the first read levelRead Level 1, generate the ECC result Res_ECC according to the ECCdecoding operation, thereby providing the ECC result Res_ECC to thefirst rewrite manager 242. The ECC result Res_ECC may include the numberof error cells Nerr. The first rewrite manager 242 may compare thenumber of error cells Nerrs with a first threshold value Nth1 that ispredetermined. The first threshold value Nth1 may be included in thefirst condition information CI_1. The first threshold value Nth1 may bea predetermined value and may be changed depending on circumstances.When the number of error cells Nerr is greater than the first thresholdvalue Nth1, the first rewrite manager 242 may determine that the firstcondition is fulfilled.

FIG. 10B describes a method of determining whether the first conditionis fulfilled when the drift occurs in the resistance distribution of thememory cells. The cell counter 280 may first perform the cell countoperation on the test data that is read according to the test readoperation by using the second read level Read Level 2 and generate thecell count result Res_CNT according to the cell count operation, therebyproviding the cell count result Res_CNT to the first rewrite manager242. The cell count result Res_CNT may include the number of on cellsNon. Here, an on cell may be a cell having a resistance value greaterthan a resistance of a reference level. The first rewrite manager 242may compare the number of on cells Non with a second threshold valueNth2 that is predetermined. The second threshold value Nth2 may beincluded in the first condition information CI_1. The second thresholdvalue Nth2 may be a predetermined value and may be changed depending oncircumstances. When the number of on cells Non is greater than thesecond threshold value Nth2, the first rewrite manager 242 may determinethat the first condition is fulfilled.

FIG. 11 illustrates a graph of a partial rewrite pulse and a normal readpulse over time according to an example embodiment. FIG. 11 particularlyillustrates a voltage pulse applied to the selected memory cell by theread/write circuit 360, in operation S128 described with reference toFIG. 9. FIG. 11 is described with reference to FIG. 8.

The first rewrite operation may also be referred to as a partial rewriteoperation. The partial rewrite pulse applied to selected memory cells inthe first rewrite operation, compared to the normal read pulse, may havea higher voltage level and a shorter duration. In other words, assumingthat the partial rewrite pulse has characteristics of a partial rewritevoltage level V_prw and a partial rewrite time duration TD_prw, thepartial rewrite voltage level V_prw may be higher than the normal readvoltage level V_nrd and the partial rewrite time duration TD_prw may beshorter than the normal read time duration TD_nrd. In an embodiment, thepartial rewrite voltage level V_prw may be higher than a reset-statethreshold voltage level Vth_reset. A change that occurs when the partialrewrite pulse is applied to the selected memory cell is described withreference to FIG. 12.

The partial rewrite pulse may have various forms. In an implementation,the voltage level of the partial rewrite pulse may be similar to orlower than the voltage level of the normal read pulse. In other words,the partial rewrite voltage level V_prw may be similar to or lower thanthe normal read voltage level V_nrd. In an implementation, the durationof the partial rewrite pulse may be equal or similar to the time periodconsumed for precharge during the normal read operation. In anembodiment, the voltage level of the partial rewrite pulse may be lowerthan a voltage level of pulses used in the write operation.

FIG. 12 illustrates a graph of a partial rewrite pulse over time, agraph of a cell current over time, and a change in the distribution,according to an example embodiment. FIG. 12 particularly shows examplesof changes that occur when the rewrite pulse shown in FIG. 11 is appliedto the memory cell. FIG. 12 is described with reference to FIG. 8. Acase in which the resistance distributions of the selected memory cellsare degraded from S1 and S2 to S1′ and S2′ is assumed.

After operations S122, S124, and S126 in FIG. 9, in operation S128, thedata operation manager 240 may apply the partial rewrite pulse to theselected memory cells. In this case, the cells to which the partialrewrite pulse is applied may include, from among the selected memorycells, the reset-state cells and the set-state cells.

When the partial rewrite pulse is applied to the selected memory cells,a current having a pointed pulse-shape, as compared to the square pulseof the partial rewrite pulse, may be temporarily formed in the selectedmemory cells. As the partial rewrite voltage level V_prw is higher thanthe reset-state threshold voltage level Vth_reset, a current having apulse-shape may be formed in the reset-state cells from among theselected memory cells. The current having the pointed pulse-shape, whichis temporarily formed in the selected memory cells, may move theresistance distribution of the set-state cells from among the selectedmemory cells from S1′ to S1′″ and move the resistance distribution ofthe reset-state cells from among the selected memory cells from S2′ toS2′″. In other words, through the first rewrite operation, the firstrewrite manager 242 may compensate for the drift occurred in the memorycell array 310.

FIG. 13 illustrates the memory system 400 according to an exampleembodiment. More particularly, FIG. 13 illustrates configurations of thememory system 400 for describing operation S160 of FIG. 7 in moredetail.

The memory controller 200 may include the second rewrite manager 244,the ECC engine 250, and the cell counter 280, and may also store thesecond condition information CI_2 and the distribution adjustmentinformation DAI.

The second rewrite manager 244 may determine the distribution adjustmentdegree by using the result of the normal read operation in operationS140 shown in FIG. 7, and may, based on the determined distributionadjustment degree, control the second rewrite operation of the memorydevice 300. In an embodiment, the ECC engine 250 may perform an ECCdecoding operation using the pieces of data read from the normal readoperation and generate an ECC result Res_ECC. The ECC engine 250 mayprovide the ECC result Res_ECC to the second rewrite manager 244. In anembodiment, the ECC result Res_ECC may include the number of the STRerror cells and the number of RTS error cells. In an embodiment, thecell counter 280 may perform a cell counter operation using the piecesof data read in the normal read operation and provide the cell countresult Res_CNT to the second rewrite manager 244. The cell count resultRes_CNT may include information regarding the number of on cells.

The second rewrite manager 244 may determine the distribution adjustmentdegree based on the ECC result Res_ECC and/or the cell count resultRes_CNT, and may control the second rewrite operation of the memorydevice 300 in accordance therewith. In an embodiment, the second rewritemanager 244 may determine the distribution adjustment degree by usingthe distribution adjustment information DAI. In an embodiment, thesecond rewrite manager 244 may determine whether the second condition isfulfilled by comparing the ECC result Res_ECC and/or the cell countresult Res_CNT with the second condition information CI_2. When thesecond condition is fulfilled, the second rewrite manager 244 maycontrol the second rewrite operation of the memory device 300.

FIG. 14 is a flowchart for describing a method of controlling the secondrewriting operation. FIG. 14 may particularly be a more detailedflowchart for describing operation S160 described with reference to FIG.7. FIG. 14 is described with reference to FIG. 13.

In operation S162, the memory controller 200 may receive the pieces ofread data according to the normal read operation from the memory device300.

In operation S164, the memory controller 200 may determine whether adistribution of the pieces of read data fulfills the second conditionthat indicates degradation of the distribution. Whether the secondcondition is fulfilled is described with reference to FIGS. 15 to 20.

In operation S166, when the second condition is fulfilled, the memorycontroller 200 may determine the distribution adjustment degree based oninformation regarding the distribution of the pieces of read data. Theinformation regarding the distribution of the pieces of read data mayinclude a degradation direction and degradation degree of the resistancedistribution. In an implementation, the information regarding thedistribution of the pieces of read data may include at least one of thenumber of STR error cells, the number of RTS error cells, and the numberof on cells.

FIG. 15 illustrates a distribution of memory cells for describing thesecond condition according to an example embodiment. FIG. 15 isdescribed with reference to FIG. 14.

The upper graph of FIG. 15 illustrates a case in which the memory cellsare degraded in the direction of a positive resistance axis. The lowergraph of FIG. 15 illustrates a case in which the memory cells aredegraded in the direction of a negative resistance axis. In FIG. 15, itis assumed that the normal read operation is a read operation using athird read level Read Level 3. The third read level may be equal orsimilar to the normal read level.

Referring to the upper graph of FIG. 15, the ECC engine 250 may identifythe number of error cells Nerr by performing the ECC decoding operationon the pieces of read data. More particularly, in the upper graph ofFIG. 15, the error cells may indicate the STR error cells converted fromthe original set-state to the reset-state.

Referring to the lower graph of FIG. 15, the ECC engine 250 may identifythe number of error cells Nerr by performing the ECC decoding operationon the pieces of read data. More particularly, in the lower graph ofFIG. 15, the error cells may indicate the RTS error cells converted fromthe original reset-state to the set-state.

The second rewrite manager 244 may compare the number of error cellsNerr with the third threshold value Nth3 that is predetermined. Thethird threshold value Nth3 may be included in the second conditioninformation CI_2. The third threshold value Nth3 may be a predeterminedvalue and may be changed depending on the occasion. When the number oferror cells Nerr is greater than the third threshold value Nth3, thesecond rewrite manager 244 may determine that the second condition isfulfilled.

FIG. 16 is a flowchart for describing a method of controlling the secondrewrite operation. FIG. 16 may, when the second rewrite operation iscontrolled using the number of error cells, particularly be a moredetailed flowchart for describing operation S166 described withreference to FIG. 14. FIG. 16 is described with reference to FIG. 14.

In operation S210, based on the ECC result Res_ECC received from the ECCengine 250, the memory controller 200 may obtain the number of STR errorcells converted from the original set-state to the reset-state and thenumber of RTS error cells converted from the original reset-state to theset-state.

In operation S220, the memory controller 200 may compare the number ofSTR error cells with the number of RTS error cells.

In operation S230, according to whether the number of STR error cells isgreater than the number of RTS error cells, different methods ofperforming the second rewrite operation may be determined. In otherwords, when there are more STR error cells than RST error cells, a setpulse may be adjusted or adapted for the second rewrite operation and,when there are more RST error cells than STR error cells, a reset pulsemay be adjusted or adapted for the second rewrite operation.

In operation S240, when the number of STR error cells is greater thanthe number of RTS error cells, the memory controller 200 may determinethe distribution adjustment degree such that the set-state cells have aresistance distribution lower than the set-state normal distribution.Operation S240 will be described in more detail with reference to FIG.18.

In operation S250, when the number of STR error cells is not greaterthan the number of RTS error cells, the memory controller 200 maydetermine the distribution adjustment degree such that the reset-statecells have a resistance distribution that is higher than the reset-statenormal distribution. Operation S250 will be described in more detailwith reference to FIG. 19.

FIG. 17 illustrates a graph of an adaptive reset pulse, an adaptive setpulse, a normal reset pulse, and a normal set pulse, according to time.FIG. 17 particularly illustrates a current applied to the selectedmemory cell by the read/write circuit 360, in operations S240 and S250described with reference to FIG. 16. FIG. 17 is described with referenceto FIG. 14.

The second rewrite operation may also be referred to as an adaptiverewrite operation. The adaptive reset pulse applied to the selectedmemory cell in the second rewrite operation may, compared to the normalreset pulse, may have a higher voltage level and a shorter duration. Inother words, assuming that the adaptive reset pulse has characteristicsof an adaptive reset current level I_ars and adaptive reset timeduration TD_ars, the adaptive reset current level I_ars may be higherthan the normal reset current level I_nrs, and the adaptive reset timeduration TD_ars may be shorter than the normal reset time durationTD_nrs. The adaptive set pulse applied to the selected memory cell inthe second rewrite operation may, compared to the normal set pulse, mayhave a lower voltage level and a longer duration. In other words,assuming that the adaptive set pulse has characteristics of an adaptiveset current level I_as and an adaptive set time duration TD_as, theadaptive set current level I_as may be lower than the normal set currentlevel I_ns, and the adaptive set time duration TD_as may be longer thanthe normal set time duration TD_ns. In an embodiment, the adaptive setcurrent level I_as may be higher than a crystallization current levelI_crys. A change occurring when the adaptive set pulse is applied to theselected memory cell is described with reference to FIG. 18 and a changeoccurring when the adaptive reset pulse is applied to the selectedmemory cell is described with reference to FIG. 19.

FIG. 18 illustrates a graph of the adaptive set pulse and fluctuation ina distribution, according to time. FIG. 18 particularly shows a changewhen the adaptive set pulse shown in FIG. 17 is applied to the memorycells. FIG. 18 is described with reference to FIG. 14. A case in whichthe resistance distributions of the selected memory cells are degradedfrom S1 and S2 to S1′ and S2′ is assumed.

After operations S210, S220, and S230 shown in FIG. 16, in operationS240, the data operation manager 240 may apply the adaptive set pulse tothe set-state memory cells, from among the selected memory cells.

When the adaptive set pulse is applied to the set-state cells from amongthe selected memory cells, the resistance distribution of the set-statecells from among the selected memory cells may move from S1′ to S11. Asa pulse having a lower level and a longer duration is applied to theset-state cells, the set-state cells may have resistance distributionlower than S1, i.e., the set-state normal distribution. In the memorycells that have moved from S1 to S1′, drifts are likely to occur in theresistance distribution. The second rewrite manager 244 according to anexample embodiment may form a distribution of the selected memory cells,considering drifts that may occur in the future, according todegradation tendency of the memory cells.

Meanwhile, the normal reset pulse may be applied to the reset-statecells from among the selected memory cells, and thus, the normal resetoperation may be performed. Accordingly, the resistance of distributionof the reset-state cells from among the selected memory cells may movefrom S2′ to S21. The resistance distribution of S21 may be equal to or alittle lower than that of S2.

FIG. 19 illustrates a graph of the adaptive reset pulse and fluctuationin a distribution, according to time. FIG. 19 particularly shows achange that occurs when the adaptive reset pulse shown in FIG. 17 isapplied to the memory cell. FIG. 19 is described with reference to FIG.14. A case in which the resistance distributions of the selected memorycells are degraded from S1 and S2 to S1″ and S2″ is assumed.

After operations S210, S220, and S230 shown in FIG. 16, in operationS250, the second rewrite manager 244 may apply the adaptive reset pulseto the reset-state cells from among the selected memory cells.

When the adaptive reset pulse is applied to the reset-state cells fromamong the selected memory cells, the resistance distribution of thereset-state cells from among the selected memory cells may move from S2″to S22. As a pulse having a higher level and a shorter duration isapplied to the reset-state cells, the reset-state cells may have aresistance distribution higher than S2, that is, the reset-state normaldistribution. Empirically, in the memory cells that have moved from S2to S2″, the resistance distribution is likely degrade in the negativedirection on the resistance axis hereinafter. The second rewrite manager244 according to an example embodiment may form a distribution of thememory cells, considering degradations that may occur later.

Meanwhile, the normal set pulse may be applied to the set-state cellsfrom among the selected memory cells, and thus, the normal set operationmay be performed. Accordingly, the resistance distribution of theset-state cells from among the selected memory cells may move from S1″to S12. The resistance distribution of S12 may be equal to or a littlehigher than that of S1.

FIG. 20 illustrates distributions of the memory cells for describing thesecond condition according to an example embodiment. FIG. 20 isdescribed with reference to FIG. 14.

The upper graph in FIG. 20 illustrates a degradation case of the memorycells corresponding to FIG. 6A, and the lower graph in FIG. 20illustrates a degradation case of the memory cells corresponding to FIG.6B.

Referring to the upper graph of FIG. 20, the cell counter 280 may, afterperforming the cell count operation on pieces of read data read from thenormal read operation according to a fourth read level Read Level 4,provide a cell count result Res_CNT to the second rewrite manager 244 bygenerating the cell count result Res_CNT according to the cell countoperation. The cell count result Res_CNT may include the number of oncells Non. The fourth read level may be higher than the normal readlevel.

The second rewrite manager 244 may compare the number of on cells Nonwith a fourth threshold value Nth4 and a fifth threshold value Nth5,which are predetermined values. The fourth threshold value Nth4 and thefifth threshold value Nth5 may be included in the second conditioninformation CI_2. The fifth threshold value Nth5 may be less than thefourth threshold value Nth4. The fourth threshold value Nth4 and thefifth threshold value Nth5 may be predetermined values and be changeddepending on the occasion. When the number of error cells Nerr isgreater than the fourth threshold value Nth4 or less than the fifththreshold value Nth5, the second rewrite manager 244 may determine thatthe second condition is fulfilled.

FIG. 21 is a flowchart for describing a method of controlling the secondrewrite operation. FIG. 21 may, when the second rewrite operation iscontrolled by using the number of on cells, particularly be a moredetailed flowchart for describing operation S166 shown in FIG. 14. FIG.21 is described with reference to FIG. 14.

In operation S310, the memory controller 200 may obtain the number of oncells, based on the cell count result Res_CNT received from the cellcounter 280.

In operation S320, depending on whether the number of on cells isgreater than the fourth threshold value Nth4, a different method ofperforming the second rewrite operation may be determined. In otherwords, when the number of on cells is greater than the fourth thresholdvalue Nth4, a set pulse may be adjusted or adapted for the secondrewrite operation, otherwise a reset pulse may be adjusted or adaptedfor the second rewrite operation

In operation S330, when the number of on cells is greater than thefourth threshold value Nth4, the memory controller 200 may determine thedistribution adjustment degree such that the set-state cells haveresistance distribution that is lower than the set-state normaldistribution. According to a result of operation S330, as shown in FIG.18, the second rewrite operation may be performed to apply the adaptiveset pulse to the set-state cells from among the selected memory cells.

In operation S340, when the number of on cells is not greater than thefourth threshold value Nth4, the memory controller 200 may determine thedistribution adjustment degree such that the reset-state cells have aresistance distribution that is higher than the reset-state normaldistribution. After the operation shown in FIG. 20, the number of oncells that is not greater than the fourth threshold value Nth4 mayindicate that the number of on cells is less than the fifth thresholdvalue Nth5. According to a result of operation S340, as shown in FIG.19, the second rewrite operation may be performed to apply the adaptivereset pulse to the reset-state cells from among the selected memorycells may be performed.

FIGS. 22A and 22B show the distribution adjustment information DAIaccording to an example embodiment. FIG. 22A particularly shows thedistribution adjustment information DAI according to the embodimentscorresponding to FIGS. 15 and 16. FIG. 22B particularly shows thedistribution adjustment information DAI according to the embodimentscorresponding to FIGS. 20 and 21.

The second rewrite manager 244 shown in FIG. 14 may determine thedistribution adjustment degree by using the distribution adjustmentinformation DAI as shown in FIGS. 22A and 22B. For example, the secondrewrite manager 244 may determine the distribution adjustment degree bycomparing the ECC result Res_ECC from the ECC engine 250 with thedistribution adjustment information DAI shown in FIG. 22A. As anotherexample, the second rewrite manager 244 may determine the distributionadjustment degree by comparing the cell count result Res_CNT from thecell counter 280, with the distribution adjustment information DAI shownin FIG. 22B.

Referring to FIG. 22A, the distribution adjustment information DAI mayinclude a table including distribution adjustment degrees eachcorresponding to a value of subtracting the number of RTS error cellsfrom the number of STR error cells. The distribution adjustment degreeof a negative number indicates performing the second rewrite operationsuch that the set-state distribution has a resistance less than that ofthe set-state normal distribution, as shown in FIG. 18. The distributionadjustment degree of a positive number indicates performing the secondrewrite operation such that the reset-state distribution has aresistance greater than that of the reset-state normal distribution, asshown in FIG. 19. Hereinafter, for convenience of explanation, the valueof subtracting the number of RTS error cells from the number of STRerror cells is referred to ‘a gap between the numbers of error cells’.

The distribution adjustment information DAI may include a plurality ofreference values Nref_11, Nref_12, . . . , Nref_1 k, Nref_21, Nref_22, .. . , Nref_2 m for determining the distribution adjustment degree. Forexample, when the gap between the numbers of error cells corresponds toa value between the reference value Nref_11 and the reference valueNref_12, the distribution adjustment agree may be determined as −DEG_11.As another example, when the gap between the numbers of error cellscorresponds to a value between the reference number −Nref_23 and thereference number −Nref_22, the distribution adjustment degree may bedetermined as +DET_22.

Referring to FIG. 22B, the distribution adjustment information DAI mayinclude a table including distribution adjustment degrees correspondingto the number of on cells. The distribution adjustment information DAImay include a plurality of reference values Nref_31, N_ref32, . . . ,Nref_3 n, Nref_41, Nref_42, . . . , Nref_4 p for determining thedistribution adjustment degree. The reference value Nref_31 may be equalto the fourth threshold value Nth4 shown in FIG. 20 and the referencevalue Nref_41 may be equal to the fifth threshold value Nth5 shown inFIG. 20. For example, when the number of on cells corresponds to a valuebetween the reference value Nref_32 and the reference number Nref_33,the distribution adjustment degree may be determined as −DEG_32. Asanother example, when the number of on cells is less than the referencevalue Nref_4 p, the distribution adjustment degree may be determined as+DET_4 p.

FIG. 23 is a flowchart for describing a controlling method of the memorycontroller. In FIG. 23, operations added to those of FIG. 7 will bemainly described. For example, operations S410, S420, S450, and S460 mayrespectively correspond to operations S120, S140, S160, and S180 shownin FIG. 7. The added operations of FIG. 23 are described with referenceto FIGS. 1 through 3.

In operation S430, the memory controller 200 may perform an ECC decodingoperation using pieces of data read according to the normal readoperation. For example, the ECC engine 250 may perform the ECC decodingoperation by using the pieces of data read from the normal readoperation.

In operation S440, according to whether the ECC decoding is successfullyperformed, different methods may be determined.

When the ECC decoding is successfully performed, operations S450 andS460 may be performed.

When the ECC decoding operation is not successfully performed, inoperation S470, the memory controller 200 may control the memory device300 by changing the read voltage level such that the memory device 300retries the read operation.

Only embodiments completed after operation S470 are described withreference to FIG. 23. In an implementation, according to a result ofoperation S470, when the ECC decoding operation is successfullyperformed after retrying the read operation, operations S450 and S460may be performed.

Embodiments provide a method performed by a memory device to rewritedata, a memory controller, a controlling method of the memorycontroller, whereby read errors due to fluctuation in a distribution ofmemory cells are reduced and control operations adaptive tocharacteristics of the memory cells are performed.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

What is claimed is:
 1. A memory controller for controlling a memorydevice, the memory controller comprising: an error checking andcorrecting (ECC) engine to perform error detection on data read from thememory device; and a data operation manager to control a first rewriteoperation of the memory device on selected memory cells to compensatefor a drift in a distribution of the selected memory cells, based on aresult of a test read operation of the memory device on test cells,determine a distribution adjustment degree based on a result of a normalread operation, as an ECC decoding operation corresponding to the normalread operation of the memory device is successfully performed by usingthe ECC engine, and control a second rewrite operation of the memorydevice based on the determined distribution adjustment degree.
 2. Thememory controller as claimed in claim 1, wherein the data operationmanager is to control the memory device to perform the test readoperation when a memory system is powered on after being powered off,the memory system including the memory device and the memory controller.3. The memory controller as claimed in claim 1, wherein the dataoperation manager is to control the memory device to perform the firstrewrite operation when the number of error cells detected in the testread operation by using a first read level is greater than a firstthreshold value or when the number of on cells according to the testread operation by using a second read level higher than the first readlevel is greater than a second threshold value.
 4. The memory controlleras claimed in claim 1, wherein the data operation manager is to controlthe memory device to apply, to the selected memory cells, a voltage of apartial rewrite pulse which has a higher level and a shorter durationthan a level and duration of a normal read pulse used in the normal readoperation.
 5. The memory controller as claimed in claim 1, wherein, whenthe set-state distribution of the selected memory cells before thesecond rewrite operation is on the right of the set-state normaldistribution along a positive resistance axis, the data operationmanager is to control the second rewrite operation such that a set-statedistribution of the selected memory cells is on the left of a set-statenormal distribution.
 6. The memory controller as claimed in claim 1,wherein, when the reset-state distribution of the selected memory cellsbefore the second rewrite operation is on the left of the reset-statenormal distribution along a positive resistance axis, the data operationmanager is configured to control the second rewrite operation such thata reset-state distribution of the selected memory cells is on the rightof a reset-state normal distribution.
 7. A controlling method of amemory controller, the method comprising: controlling, based on a resultof a test read operation on test cells included in a memory device, afirst rewrite operation of the memory device to compensate for a driftof a distribution of selected memory cells; controlling a normal readoperation of the memory device on the selected memory cells, the normalread operation using a normal read pulse; and controlling, based on adistribution adjustment degree determined according to a result of thenormal read operation, a second rewrite operation of the memory deviceon the selected memory cells.
 8. The method as claimed in claim 7,wherein controlling the first rewrite operation includes: transmitting aread command for the test cells to the memory device; receiving, fromthe memory device, pieces of test data corresponding to the readcommand; determining whether a distribution of the pieces of test datafulfills a first condition indicating degradation of the distribution;and when the first condition is fulfilled, controlling the memory deviceto perform the first rewrite operation.
 9. The method as claimed inclaim 8, wherein determining whether the distribution of the pieces oftest data fulfills the first condition includes determining whether thenumber of error cells detected from the test read operation by using afirst read level is greater than a first threshold value.
 10. The methodas claimed in claim 8, wherein determining whether the distribution ofthe pieces of test data fulfills the first condition includesdetermining whether the number of on cells according to the test readoperation using a second read level is greater than a second thresholdvalue.
 11. The method as claimed in claim 8, wherein controlling thememory device to perform the first rewrite operation includescontrolling the memory device to apply a partial rewrite pulse, whichhas a higher voltage level and a shorter duration than the normal readpulse, to the selected memory cells.
 12. The method as claimed in claim7, wherein the controlling the second rewrite operation includes:receiving pieces of read data according to the normal read operation;determining whether a distribution of the pieces of read data fulfills asecond condition indicating degradation of the distribution; anddetermining the distribution adjustment degree as the second conditionis fulfilled, based on information regarding the distribution of thepieces of read data.
 13. The method as claimed in claim 12, whereindetermining whether the distribution of the pieces of read data fulfillsthe second condition includes determining whether the number of errorcells detected in the normal read operation is greater than a thirdthreshold value.
 14. The method as claimed in claim 13, whereindetermining the distribution adjustment degree includes: obtaining,based on an ECC result provided from the ECC engine, a number of firsterror cells converted from an original set-state to a reset-state and anumber of second error cells converted from an original reset-state to aset-state; comparing the number of first error cells to the number ofsecond error cells; when the number of first error cells is greater thanthe number of second error cells, determining the distributionadjustment degree such that set-state cells from among the selectedmemory cells have a resistance distribution having a level that is lowerthan a set-state normal distribution; and when the number of first errorcells is not greater than the number of second error cells, determiningthe distribution adjustment degree such that reset-state cells fromamong the selected memory cells have a resistance distribution having alevel higher than a reset-state normal distribution.
 15. The method asclaimed in claim 14, wherein, when the number of first error cells isgreater than the number of second error cells, controlling the secondrewrite operation further includes controlling the memory device toapply, to the set-state cells from among the selected memory cells, apulse corresponding to an adaptive set pulse having at least one of alower current level and a longer duration than that of the normal setpulse.
 16. The method as claimed in claim 14, wherein, when the numberof first error cells is not greater than the number of second errorcells, controlling of the second rewrite operation further includescontrolling the memory device to apply, to reset-state cells from amongthe selected memory cells, a current corresponding to an adaptive resetpulse having at least one of a higher current level and a shorterduration than that of the normal reset pulse.
 17. The method as claimedin claim 12, wherein determining whether the distribution of the piecesof read data fulfills the second condition comprises determining whethera number of on cells corresponding to the normal read operation isgreater than a predetermined fourth threshold value or less than apredetermined fifth threshold value, the fifth threshold value beingless than the predetermined fourth threshold value.
 18. The method asclaimed in claim 17, wherein determining the distribution adjustmentdegree includes: obtaining the number of on cells based on a cell countresult provided from a cell counter; when the number of on cells isgreater than the fourth threshold value, determining the distributionadjustment degree such that set-state cells from among the selectedmemory cells have a resistance distribution lower than a set-statenormal distribution; and when the number of on cells is less than thefifth threshold value, determining the distribution adjustment degreesuch that reset-state cells from among the selected memory cells have aresistance distribution higher than a reset-state normal distribution.19. A method of rewriting data of a memory device, the methodcomprising: performing, on selected memory cells, a normal data writeoperation including a normal reset operation to form a reset-statenormal distribution using a normal reset pulse and a normal setoperation to form a set-state normal distribution using a normal setpulse; when a drift in a distribution of the selected memory cells isdetected according to a test read operation on test cells, performing apartial rewrite operation on the selected memory cells to compensate forthe drift; performing a normal read operation on the selected memorycells using a normal read pulse; determining a direction of degradationin the distribution of the selected memory cells from the normal readoperation; and performing, based on the reset-state normal distributionand the set-state normal distribution, an adaptive rewrite operation toform distributions shifted in a direction opposite the determineddirection of the degradation.
 20. The method as claimed in claim 19,wherein performing of the adaptive rewrite operation includes: when thenumber of first error cells converted from an original set state to areset state is greater than the number of second error cells convertedfrom an original reset state to a set state, applying, to set-statecells from among the selected memory cells, a current corresponding toan adaptive set pulse having at least one of a lower current level and alonger duration than the normal set pulse; when the number of firsterror cells is not greater than the number of second error cells,applying, to reset-state cells from among the selected memory cells, acurrent corresponding to an adaptive reset pulse having at least one ofa higher current level and a shorter duration than the normal resetpulse.